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TC18C46 TC28C46 TC38C46 CMOS CURRENT MODE PWM CONTROLLER
FEATURES
s s s s s s s s s s s s s s s s s s s Isolated Output Drive Low Power CMOS Construction Low Supply Current ................................. 2mA Typ. Wide Supply Voltage Operation .............. 8V to 18V Latch-Up Immunity ................... 500mA on Outputs Above and Below Rail Input Protection ............. 6V High Output Drive ................................ 500mA Peak Current Mode Control Fast Rise/Fall Time ..................... 50nsec @ 1000pF High Frequency Operation .......................... 500kHz UV Hysteresis Guaranteed Programmable Current Limit Shutdown Pin Available Double Ended Soft Start Low Prop Delay Current Amp to Output ......................................... < 350nsec Typ. Low Prop Delay Shutdown to Output ......................................... < 400nsec Typ. TC38C46Pin Compatible with Unitrode UC3846 ESD Protected ................................................. 2 kV
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GENERAL DESCRIPTION
The TC38C46 is a current mode CMOS PWM control IC. It draws only 2 mA supply current, so it can be driven without a costly 50-60 Hz transformer. The output drive stage is capable of high drive currents, 300mA typical. The TC38C46 is pin compatible with earlier bipolar products so that designers can easily update older designs. A number of improvements have been added. This second generation part has been designed with an isolated drive stage. Unlike its cousin, the TC170, the output stage of the TC38C46 can be run from a separate power supply such as a secondary winding on an output transformer. This allows for bootstrap start-up of the power supply.
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ORDERING INFORMATION
Part No. TC18C46MJE TC28C46EOE TC28C46EPE TC38C46COE TC38C46CPE Configuration Non-Inverting Non-Inverting Non-Inverting Non-Inverting Non-Inverting Pkg./Temperature 16-Pin CerDIP - 55C to +125C 16-Pin SOIC (Wide) - 40 C to +85C 16-Pin Plastic DIP (Narrow) - 40C to +85C 16-Pin SOIC (Wide) 0C to +70C 16-Pin Plastic DIP (Narrow) 0C to +70C
FUNCTIONAL BLOCK DIAGRAM
VREF 2 VIN RT CT SYNC - CURRENT SENSE INPUT + CURRENT SENSE INPUT COMPENSATION 15 9 8 10 3 4 7 + +VS + ERROR AMP INPUT - ERROR AMP INPUT 5 6 + - ERROR AMPLIFIER 100A LIMIT BUFFER AMPLIFIER Q4 + - 350mV LOCK-UP AMPLIFIER Q3 TC18C46 TC28C46 TC38C46 3.5k Q1 - + POSITIVE FEEDBACK Q2 6k SHUTDOWN COMPARATOR + - 350mV 16 CURRENT SENSE PWM AMPLIFIER COMPARATOR .65V - + x3 -+ + - R Q S S PWM LATCH 14 12 OSCILLATOR UNDER VOLTAGE LOCKOUT DQ CQ 5.1 VOLT REFERENCE 13 11
VDD OUTPUT A
OUTPUT B GROUND
1
7
CURRENT LIMIT SOFT START ADJUST SHUTDOWN TC38C46 OUTPUTS LOW IN OFF STATE
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
ABSOLUTE MAXIMUM RATINGS
Output Current, Source or Sink (Pins 1, 14) ..........500mA Analog Inputs (Pins 3, 4, 5, 6, 16) .............. - 0.3V to +VIN Reference Output Current (Pin 2) ........................ - 30 mA Sync Output Current (Pin 10) .................................. - 5mA Error Amplifier Output Current (Pin 7) ..................... - 5mA Soft Start Sink Current (Pin 1) .................................. 50mA Oscillator Charging Current (Pin 9) ............................5mA Supply Voltage ............................................................18V Maximum Chip Temperature ................................... 150C Storage Temperature ............................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................... 300C Package Thermal Resistance CerDIP RJ-A ................................................................. 150C/W CerDIP RJ-C ................................................................... 55C/W PDIP RJ-A ..................................................................... 125C/W PDIP RJ-C ........................................................................ 45C/W SOIC RJ-A ..................................................................... 250C/W SOIC RJ-C ....................................................................... 75C/W
NOTES: 1. All voltages are with respect to Ground, Pin 12. Currents are positive into, negative out of the specified terminal. 2. Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS 16-Pin Plastic DIP (Narrow) 16-Pin CerDIP
CURRENT LIMIT/ SOFT START VREF - CURRENT SENSE + CURRENT SENSE + ERROR AMP - ERROR AMP COMP CT 1 2 3 4 5 6 7 8 TC18C46MJE TC28C46EPE TC38C46CPE 16 15 14 13 12 11 10 9 SHDN VIN OUTPUT B VDD GND OUTPUT A SYNC RT CURRENT LIMIT/ SOFT START VREF - CURRENT SENSE + CURRENT SENSE + ERROR AMP - ERROR AMP COMP CT
16-Pin SOIC (Wide)
1 2 3 4 5 6 7 8 TC28C46EOE TC38C46COE
16 15 14 13 12 11 10 9
SHDN VIN OUTPUT B VDD GND OUTPUT A SYNC RT
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
ELECTRICAL CHARACTERISTICS: unless otherwise stated, these specifications apply for TA = - 55C to +125C for TC18C46; - 40C to +85C for the TC28C46; and 0C to +70C for the TC38C46; VIN = VDD = 16V; RT = 30.1k; CT = 270pF.
TC18C46 TC28C46 Parameter Reference Section
Output Voltage Line Regulation Load Regulation Temp Coefficient Total Output Range Long Term Drift Short Circuit Output Current Output Noise Voltage Tf = 25C, IO = 1mA VIN = 8V to 16V IO = 1mA to 10mA Over Operating Range, (Note 1) Line, Load, and Temperature (Note 1) Tf = 125C, 1000 Hrs (Note 1) VREF = 0V 10 Hz f 10 kHz, Tf = 25C (Note 1) Tf = 25C VIN = 8V to 16V Over Operating Range (Note 1) 5.0 -- -- -- 4.97 -- 20 -- 96.5 -- -- 1.2 3.6 VDD -0.5 -- -- -- -- -- -- -- 70 0.7 70 70 2 5 4.75 -- 1.3 5.1 4 4 0.2 -- 50 -- 22 102 .1 .04 2 3.8 -- -- 8.5 8.5 5 5 10 10 90 1 90 90 4 10 4.9 0.4 2 5.2 20 20 0.5 5.24 -- 70 -- 106.5 2.0 0.06 3 4 -- 0.5 -- 5 50 25 100 100 -- -- -- -- -- -- 5.1 0.9 -- 5.0 -- -- -- 4.94 -- 20 -- 96.5 -- -- 1.2 3.6 VDD -0.5 -- -- -- -- -- -- -- 70 0.7 70 70 2 5 4.75 -- 1.3 5.1 4 4 0.2 -- 50 -- 22 101 .1 .04 2 3.8 -- -- 8.5 8.5 5 5 0.1 0.1 90 1 90 90 4 10 4.9 0.4 2 5.2 20 20 0.5 5.26 -- 70 -- 106.5 1.5 0.06 3 4 -- 0.5 -- 5 50 25 0.5 0.5 -- -- -- -- -- -- 5.1 0.9 -- V mV mV mV/C V mV mA V(rms) kHz %/V %/C mA V V V V V nA mV nA nA dB MHz dB dB mA mA V V V/sec
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TC38C46 Max Min Typ Max Units
Test Conditions
Min
Typ
Oscillator Section
Initial Accuracy Voltage Coefficient Temp Coefficient Clock Ramp Reset Current Osc Ramp Amplitude Sync Output High Level Sync Output Low Level Sync Input High Level Sync Input Low Level Sync Input Current
(Note 1) (Note 1) Pin 8 = 0V, (Note 1) Pin 8 = 0V, (Note 1) Sync Voltage = 5.25V, Pin 8 = 0V
Error Amp Section
Input Offset Voltage Input Bias Current Input Offset Current Open Loop Voltage Gain Gain Bandwidth Product CMRR PSRR Output Sink Current Output Source Current High Level Output Volt Low Level Output Volt Slew Rate
VO = 1V to 6V, RL = 100k Tf = 25C (Note 1) VCM = 0V to 11V VIN = 8V to 16V V(EA -) = 5V, V(EA+) = 4.9V, V(CMPTR) = 1.2V V(EA -) = 5V, V(EA+) = 5.1V, V(CMPTR) = 2.5V RL = (CMPTR) 5k to GND, ACL = 300 RL = (CMPTR) 5k to GND, ACL = 300
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ELECTRICAL CHARACTERISTICS (Cont): Unless otherwise stated, these specifications apply for
TA = -55C to +125C for TC18C46; - 40C to +85C for the TC28C46; and 0C to +70C for the TC38C46; VIN = VDD = 16V; RT = 30.1k; CT = 270pF. TC18C46 TC28C46 Parameter Current Sense Section
Amplifier Gain Max Differential Input Signal (VPin 4-VPin 3) Input Offset Voltage CMRR PSRR Input Bias Current Input Offset Current Input Common Mode Range Delay to Outputs (Notes 2, 3) (Note 2) (Note 2) VCM = 1V to 12V, (Note 2) VIN = 8V to 16V, (Note 2) (Note 1) (Note 1) (Note 1) Tf = 25C, (Note 1) -- (Shutdown Unlatched) 2.7 1.1 0.4 40 40 -- -- 0 150 1 3 320 0 140 -- 100 125 3 1.5 0.65 60 60 1 0.1 -- 225 25 3.5 360 -- -- -- 50 250 3.6 1.8 0.85 -- -- 100 2 11 400 -- 4 400 VIN -- 60 -- 400 2.7 1.1 0.4 40 40 -- -- 0 150 1 3 320 0 140 -- 100 125 3 1.5 0.65 60 60 1 0.1 -- 225 25 3.5 360 -- -- -- 50 250 3.4 1.8 0.85 -- -- 100 2 11 400 mV 4 400 VIN -- 65 -- 400 V/V V V dB dB nA nA V nsec
TC38C46 Max Min Typ Max Units
Test Conditions
Min
Typ
Current Limit Adjust Section
Current Limit Voltage Offset Input Impedance k mV V A A nsec nsec nsec nsec V V V mA A
Shutdown Terminal Section
Threshold Voltage Input Voltage Range Min Latching Current (IPin 1) Max Non-Latching Current (IPin1) Min Pulse Width Delay to Outputs (Note 1) (Note 4) (Note 5) (Note 1) (Note 1)
Output Section
Output Low Level rDS (ON) Output High Level rDS (ON) Output Rise Time Output Fall Time ISINK = 20mA ISOURCE = 20mA CL = 1 F CL = 1 F -- -- -- -- 6.5 7.4 0.6 -- -- 10 20 55 55 7 7.8 0.8 1.2 250 20 35 90 90 7.3 8 1 2.5 350 -- -- -- -- 6.5 7.4 0.6 -- -- 10 20 55 55 7 7.8 0.8 1.2 250 20 35 90 90 7.3 8 1 2 350
Undervoltage Lockout Section
Undervoltage Threshold Start Threshold Threshold Hysteresis
Total Standby Current
Supply Current Start-Up Current
NOTES: 1. These parameters, although guaranteed over the recommended operating conditions, are not tested in production. 2. Parameter measured at trip point of latch with VPin 6 = VREF, VPin 16 = 0V. 3. Amplifier gain is defined as: 4-104
G = VPin 7 ;VPin 4 = 0V to 1V VPin 4 4. Current into Pin 1 guaranteed to latch circuit in shutdown state. 5. Current into Pin 1 guaranteed not to latch circuit in shutdown state.
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
Peak Current Limit Setup
Resistors R1 and R2 at the CURRENT LIMIT input (pin 1) set the peak current limit (Figure 1). The potential at pin 1 is easily calculated: V1 = VREF R2 R1 + R2 The input pulse to pin 16 should be at least 100nsec wide and have an amplitude of at least 1V in order to get the minimum propagation delay from input to output. If these parameters are met, the delay should be less than 400nsec at 25C; however, the delay time will increase as the device temperature rises.
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Soft Restart From Shutdown
A soft restart can be programmed if nonlatched shutdown operation is used. A capacitor at pin 1 will cause a gradual increase in potential toward V1. When the voltage at pin 1 reaches 0.75V, the PWM latch set input is removed and the circuit establishes a regulated output voltage. The soft-start operation forces the PWM output drivers to initially operate with minimum duty cycle and low peak currents. Even if a soft start is not required, it is necessary to insert a capacitor between pin 1 and ground if the current IL is greater than 140A. This capacitor will prevent "noise triggering" of the latch, yet minimize the soft-start effect.
R1 should be selected first. The shutdown circuit feature is not latched for (VREF - 0.35)/R1 <65A and is latched for currents greater than 140A. The error amplifier output voltage is clamped from going above V1 through the limit buffer amplifier. Peak current is sensed by RS and amplified by the current amplifier which has a fixed gain of 3. IPCL, the peak current limit, is the current that causes the PWM comparator noninverting input to exceed V1, the potential at the inverting input. Once the comparator trip point is exceeded, both outputs are disabled. IPCL is easily calculated: IPCL = where: V1 = VREF R2 R1 + R2 V1 - 0.65V 3 (RS)
Soft-Start Power-Up
During power-up, a capacitor at R1, R2 initiates a softstart cycle. As the input voltage (pin 15) exceeds the under-voltage lockout potential (7V), Q4 is turned OFF, ending undervoltage lockout. Whenever the PWM comparator inverting input is below 0.65V, both outputs are disabled. When the undervoltage lockout start threshold is exceeded, the capacitor begins to charge. The PWM duty cycle increases until the operating output voltage is reached. Soft-start operation forces the PWM output drivers to initially operate with minimum duty cycle and low peak current.
VREF = Internal voltage reference = 5.1V 3 = Gain of current-sense amplifier 0.65V = Current limit offset Both driver OUTPUTs (pins 11 and 14) are OFF (LOW) when the peak current limit is exceeded. When the sensed current goes below IPCL, the circuit operates normally.
Output Shutdown
The outputs can be turned OFF quickly through the SHUTDOWN input (pin 16). A signal greater than 360 mV at pin 16 forces the shutdown comparator output HIGH. The PWM latch is held set, disabling the outputs. Q2 is also turned ON. If VREF/R1 is greater than 140A, positive feedback through the lock-up amplifier and Q1 keeps the inverting PWM comparator inverting input below 0.65V. Q3 remains ON even after the shutdown input signal is removed. This is because the lock-up amplifier is in latched mode driving Q3 ON. This state can be cleared only through a power-up cycle. Outputs will be disabled whenever the potential at pin 1 is below 0.65V. The shutdown terminal gives a fast, direct way to disable the PWM controller output transistors. System protection and remote shutdown applications are possible. TELCOM SEMICONDUCTOR, INC.
Current-Sense Amplifier
The current-sense amplifier operates at a fixed gain of 3. Maximum differential input voltage (VPIN4-VPIN3) is 1.1V. Common-mode input voltage range is 0V to VIN - 3V. Resistive-sensing methods are shown in Figure 2. In Figure 2(A), a simple RC filter limits transient voltage spikes at pin 4, caused by external output transistor-collector capacitance. Transformer coupling (Figure 3) offers isolation and better power efficiency, but cost and complexity increase. In order to minimize the propagation delay from the input to the current amplifier to the output terminals, the current ramp should be in the order of 1sec in width (min). Typical time delay values are in the 225nsec region at 25C. The delay time increases with device temperature so that at 50C, the delay times may be increased by as much as 100nsec.
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
SWITCH CURRENT x 3 CURRENT-SENSE AMPLIFIER 4 3 RS 7 VDD 100A ERROR AMPLIFIER 5 6 + - V1 + - LIMIT BUFFER AMPLIFIER Q3 350mV - Q1 + TC18C46 TC28C46 TC38C46 POSITIVE FEEDBACK Q2 - SHUTDOWN COMPARATOR + 6k 350mV IL 3.5k 16 Q4 + - PWM COMPARATOR - + + S - FROM UNDERVOLTAGE LOCKOUT S PWM LATCH VREF 5.1V 2 R1 1 V1 Q R 10
"A" = 1 OUTPUT OFF (LOW)
0.65V
R2
LOCK-UP AMPLIFIER
Figure 1. R1 and R2 Set Maximum Peak Output Current
I x 3 CURRENTSENSE AMPLIFIER
RS VOUT
x 3 CURRENTSENSE AMPLIFIER
I + - 4 C 3 *OPTIONAL RC FILTER R* RS
+ - TCx8C46
4
3
TCx8C46
(A) Ground Reference
(B) Above-Ground Resistive Sensing
Figure 2. Resistive Sensing
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
1
x 3.15 CURRENT- SENSE AMPLIFIER + - TCX8C46 4 + VS - I * RS VS = S N
9
N 1 IS
RT TCx8C46
2
SYNC 10 CMPTR 7 1/2 TC4427
3
8C T MASTER
Figure 3. Transformer Isolated Current Sense
VDD
3
7 CMPTR
Under Voltage Lockout
The under voltage lockout circuit forces the PWM controller outputs OFF (LOW) if the supply voltage is below 7V. Threshold hysteresis is 0.8V and guarantees clean, jitterfree turn-ON and turn-OFF points. The hysteresis also reduces capacitive filtering requirements at the PWM controller supply input (pin 15).
9R T 8 CT SLAVE 2 VREF 10 SYNC
TCx8C46
4 5
Circuit Synchronization
Current-mode-controlled power supplies can be operated in parallel with a common load. Paralleled converters will equally share the load current. Voltage-mode controllers unequally share the load current, decreasing system reliability. Two or more of these PWM controllers can be slaved together for parallel operation. Circuits can operate from a master PWM controller internal oscillator with an external driver (Figure 4). Devices can also be slaved to an external oscillator (Figure 5). Disable internal slave device oscillators by grounding pin 8. Slave controllers derive an oscillator from the bidirectional synchronization output signal at pin 10. Pin 10 is bidirectional in that it is intended to be both a sync output and input. This is accomplished by making the output driver "weak." This is advantageous in that it eliminates an additional pin from the package but does not enable the device to directly drive another device. In order to make it an effective driver, a buffer is required (Figure 4). In order to use pin 10 as a sync input, it is necessary to overcome the internal driver. This requires a pulse with an amplitude equal to VS. Since VS must be above 7V for the undervoltage lockout to be disabled, a CMOS or opencollector TTL driver should be used.
Figure 4. Master/Slave Parallel Operation
VDD
15 EXTERNAL* OSCILLATOR 1/2 TC4427 10 8 TCx8C46 CT SYNC VREF RT 2 VDD 15 *PULSE WIDTH OF OSCILLATOR IS = TD 10 SYNC TCx8C46 C T VREF 2 RT 9 9
6 7
Figure 5. External Clock Synchronization
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
1/FO VDD PIN 8 TD
0.5V 3.5V
ICHARGE
3.5V RO RT
+ -
3.5V PIN 10
TCHG
10 SYNC DISCHARGE CURRENT 2mA
8
9 RT
OUTPUT DEAD TIME (TD)
CT
Figure 6. Oscillator Circuit
Selection of Timing Capacitor and Resistor (CT & RT)
1) First determine the frequency of operation FO and the desired " dead" time", TD (see Fig.6 graph). We need to choose RT and CT.
Substituting and rearranging, CT = TD 3 (.002 - 3.5) RT
Knowing TD choosing RT permits calculation of CT .
2)
The current mirror in Fig. 6 , shows: ICHG = 3.5 V RT ICHG = CT . Also,
V T
Where, and
V = 3.5 - 0.5 = 3.0 Volts T = TCHG
3)
During discharge (TD), the discharge current pulls 2 m A out of CT, minus the ICHG that keeps trying to charge it: 2 m A - ICHG = CT V T ,where V= 3.0 Volts T= TD
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
TYPICAL CHARACTERISTICS
18C46 Dead Time vs. Ct
11000 10000 Dead Time (nsec) 8000 7000 6000 5000 4000 3000 2000 1000 0 1000 2000 3000 4000 5000 Ct, pF 2k 100k 10k Dead Time (nsec) 9000 11000 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1000pF 500pF 100pF 20 40 60 Rt, k 80 100 2200pF 4700pF
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18C46 Dead Time vs. Rt
2 3 4 5
18C46 OSC Frequency vs. Ct
400 350 2k 300 FOSC, KHz FOSC, KHz 250 200 150 100 50 0 1000 2000 3000 4000 5000 Ct, pF 10k 100k 300 250 200 400 350
18C46 OSC Frequency vs. Rt
100pF
500pF 150 100 50 0 20 40 60 Rt, k 80 100 1000pF 2200pF 4700pF
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CMOS CURRENT MODE PWM CONTROLLERS TC18C46 TC28C46 TC38C46
PIN DESCRIPTION
Pin No.
1
Symbol
Description
Pin for setting the peak current limit threshold of sense inputs pin 3 and pin 4. A second function of this pin is for Soft-Start programming with a capacitor between this pin and ground, pin 12. Pin is an output for the reference supply voltage of 5.1 volts. This reference can supply a minimum of 20mA of output current. Pin is the current sense inverting input for sensing peak current of the pass transistor through the series current monitor resistor. Pin is the non-inverting input for sensing peak current of the pass transistor. The positive end of the current sense resistor is connected here. Pin is the non-inverting input for sensing voltage feedback from output for voltage regulation. Pin is the inverting input for sensing the reference voltage to regulate the output. Pin for compensating the feedback loop response. Pin is the input for timing capacitor, CT, to set oscillator frequency in conjunction with 9 resistor RT, input. A second function is for setting the crossover dead time of the outputs, pins 11 and 14. Pin is the input for the timing resistor, RT, to set oscillator frequency by setting the (constant) current charge rate for capacitor CT. Pin is the input or output for the oscillator synchronization pulse. Pin is the output drive of phase A to drive push pull transistor A. Pin is the ground return path for all input and output signals. Pin is the supply power input terminal for the output drivers. Pin is the output drive of phase B to drive push pull transistor B. Pin is voltage bias supply input for all circuits except the output drivers Pin is an input for shutdown when a 350mV threshold is exceeded: both output drives will then be terminated.
CURRENT LIMIT, SOFT START
2 3 4 5 6 7 8
VREF - CURRENT SENSE + CURRENT SENSE + ERROR AMP - ERROR AMP COMPENSATION CT
9 10 11 12 13 14 15 16
RT SYNC OUTA GND VDD OUTB VIN SHUT
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